1. Field of the Invention
The present invention relates to a layout method of a semiconductor integrated circuit provided with a decoupling capacitance for preventing malfunction caused by noises of power supply, also relates to a computer program product for causing a computer to execute such a layout method.
2. Description of Related Art
In recent years, microfabrication and high integration of a semiconductor integrated circuit have been achieved, and in connection with this, a lowering in operating voltage, an increase in speed of operating frequency, and the like have been made. For example, a process rule of manufacturing the semiconductor integrated circuit has been reduced to 0.1 μm or less, and in connection with this, an operating voltage of the semiconductor integrated circuit has also been lowered to 1.2 V or less, while the operation frequency has been increased to hundreds of MHz or more. In the semiconductor integrated circuit, however, noises are increased according to an increase in speed of operation frequency, and resistance against the noises is deteriorated by lowering voltage, thus causing a problem that circuit malfunction is easily generated by the noises.
Meanwhile, in order to prevent the circuit malfunction by the noises, there is known a technology of providing a decoupling capacitance between circuit power supplies. Conventionally, a placement of the decoupling capacitances at a CAD stage in a layout design has been performed into free areas where functional cells have not been placed after functional cells, such as flip-flops, logic gate elements, clock buffers, and I/O cells, have been first placed in a chip according to an appropriate rule. In this case, after the functional cells and the decoupling capacitances have been placed, it is necessary to verify whether or not a sufficient amount of decoupling capacitance is placed. As a result of verification, if the decoupling capacitance has not been sufficiently placed, the placement of the functional cell has been needed to be changed so that the free areas for placing the decoupling capacitance might be extended.
According to Japanese Patent Application Laid-Open No. 2004-055954, there is proposed a layout method of a semiconductor integrated circuit, in which a decoupling capacitance required for reducing a noise is estimated in advance, and as a result of that, the required decoupling capacitance is preferentially placed in a corner area which may a dead space of a chip, and a periphery of an I/O cell, and a semiconductor integrated circuit placed in such a method.
Moreover, according to Japanese Patent Application Laid-Open No. 2002-288253, there is proposed a method, in which after functional cells are placed in a chip, the chip is divided into a plurality of areas, and a required decoupling capacitance is determined for every divided area, so that the decoupling capacitance is placed in each of the areas by increasing or reducing each of the areas depending on the required amount of decoupling capacitance.
In the conventional technology for placing the conventional decoupling capacitance, however, as described above, the decoupling capacitance has been placed in free areas after the functional cells have been placed. Meanwhile, in a layout method of a semiconductor integrated circuit described in the aforementioned Japanese Patent Application Laid-Open No. 2004-055954, the decoupling capacitance is intended to be placed in a corner area of the chip, and a periphery an I/O cell. For this reason, since the decoupling capacitance is not necessarily placed near a functional cell which particularly requires the decoupling capacitance, for example a functional cell which becomes a source of power supply noise, such as a flip-flop, a clock buffer, or the like, there is a fear that the decoupling capacitance may not effectively function.
Furthermore, in a conventional art, for example, a method of placing a decoupling capacitance described in the aforementioned Japanese Patent Application Laid-Open No. 2002-288253, after a functional cells are first placed in a chip, a decoupling capacitance is placed. For this reason, when there is a shortage of a free area for placing a decoupling capacitance, it is necessary to correct the result of layout processing in order to secure the free area, so that there is a problem of an increase in time required for layout operations.